1	Rapid Prototyping Planning Updated 12/10/2007, David Farrell, CEPD, Inc.
2	Agenda Identify risks and a risk mitigation plan up front Develop a timeline Assign staff to perform tasks in parallel where feasible Minimize task dependencies Never slip a timeline date or milestone arbitrarily A Monday release is not the same as a Friday release, many subcontractors will work over the weekend on your Friday release There is nothing wrong with being ahead of schedule on unlinked tasks Some tasks will take less than planned, but others will take more, if you don’t take advantage of completing those that can be finished early, the overall schedule will slip Utilize in house resources as much as possible Only design in components if they are in stock at distributors If the distributor’s web site is not up to date, it is best to call to confirm Avoid BGAs and QFNs, they create difficulty for prototyping Order tools, evaluation boards and parts as soon as possible Expedite shipping Expedite PCB fabrication
3	Risk Mitigation Possibilities Utilize a known, working reference design Develop multiple solutions in parallel Line-up FAE/vendor support Get buy-off from customer that item is a risk (in writing/email) Early prototypes and/or do riskiest things first, before they become critical path If risk is too high, stop work and reassess project scope
4	Assign staff to perform tasks in parallel where feasible All project team members participate in system design review Interface control documentation is developed Separate project team members are assigned to each circuit card Separate project team members are assigned to each design discipline Design is phased to allow parallelism between milestones
5	Parallel Tasking Continued Within the high level design there are tasks that are done in parallel Derived hw requirements Derived sw requirements Derived mechanical requirements Within the detailed design there are tasks that are done in parallel Schematic Capture PLD/FPGA HDL Coding Software Coding Mechanical Drawing
6	Requirement vs. derived requirement Example: Requirements: Product must run from battery for 5 hours Battery is 5V, 5AHr Derived requirements: Unit must not pull more than 1A from the battery Unit must not consume more than 5W
7	Minimize Task Dependencies Remove the dependency for synthesis tools to choose the pin out of FPGAs or PLDs assign I/O for similar functions in the same banks Assign specialized pins such as global clocks, DPLLs, LVDS, SERDES, etc. distribute spares in each bank allow for schematic capture in parallel with HDL coding
8	Minimize Task Dependencies Remove dependency for working hardware prior to PLD/FPGA verification code small pieces at a time utilize a “test bench” to test HDL modules allow for schematic capture in parallel and independent of HDL coding Remove dependency for working hardware prior to software verification code small pieces at a time unit test with either a PC compiler or an evaluation board allow for schematic capture in parallel and independent of software coding
9	High Level Design Timeline Example
10	High Level Design Timeline Continued
11	Project Timeline Continued
12	The process is iterative
13	Production Timeline